HBM bandwidth acceleration

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Overview

The Ziptilion-BW, ZeroPoint’s bandwidth acceleration IP core, packages a novel and proprietary technology that accelerates the limited off-chip bandwidth of main memories through line speed, and high-performance memory data compression. The product benefit is up to 50% more main memory bandwidth at unmatched power efficiency.

Standards

  • Compression: ZID (proprietary)

  • Interface: AXI4, CHI•

  • Plug in compatible with industry standard memory controllers

Architecture

  • Real-time training to maintain optimal compression performance

  • Real-time analysis to mitigate negative throughtput impact when applications perform challenging random memory access behaviour

  • Verified maintained performance in configurations when the core to memory controller ratio is high (>100 cores).

HDL Source Licenses

  • Synthesizable System Verilog RTL (encrypted)

  • Implementation constraints

  • UVM testbench (self-checking)

  • Vectors for testbench and expected results

  • User Documentation

Features

  • Turn key solution: compression, compaction, memory management

  • Transparent addressing to operating system and applications

  • Cache line granularity to enable high throughput and low latency

Deliverables

  • Performance evaluation license C++ compression model for integration in customer performance simulation model

FPGA evaluation license

  • Encrypted IP delivery (Xilinx)

Applications

Server xPUs, Smart devices, and Embedded systems all face the same challenge. The memory bandwidth is limiting the system scaling and the many cores and accelerators are fighting to serve their memory access requests. A wide range of data sets from these different applications have been evaluated and they all verify that bandwidth acceleration provides a very efficient and effective way to utilize the full memory potential.

Integration

Ziptilion™-BW is integrated into the memory subsystem of the SoC, close to the memory controller. Intercepting the memory traffic to/from DRAM to compress and decompress data on-the-fly. The effect of compression is transparent to the xPU subsystem as well as to the operating system and applications. Similarly, the memory controller is also unaware that the transmitted/received memory data is compressed. In essence, data compression and decompression, compaction as well as addressing the compressed memory space are handled automatically, transparently, and hardware-accelerated by the IP.

Ziptilion™-BW is compatible with all DRAM technologies and supports standard interfaces such as AXI4 and CHI. Other proprietary interfaces can be supported upon request.

Certain features and sizes of the IP can be customized during the pre-silicon implementation, while post-silicon IP configuration is eligible through the provided device driver.

Benefits

High performance and low latency main memory bandwidth acceleration of 25% on average, with a peak of 50%. Unmatched power efficiency. Real-time compression, super-fast compaction, and transparent memory management. Operating at main memory speed and throughput. Compatible with AXI4/CHI, both 128b and 256b bus interface. Intelligent real-time analysis and tuning of the IP Block.

Performance / KPI

FeaturePerformance
Compression ratio:2-3x across diverse data sets
Bandwidth acceleration:25-50%
Performance acceleration:5-30%
Frequency:DDR4/DDR5 DRAM speed
IP area:Starting at 0.3mm2 (@5nm TSMC)
Memory technologies supported:(LP)DDR4, (LP)DDR5, HBM

System integration with Ziptilion-BW

Ziptilion-BW is integrated on the memory access path, intercepting the data sent to and from memory. Depending on the application (Server CPU, GPU, xPU, or Smart devices) the preferred interfaces are AXI4 and CHI.

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High Performance and Low Latency AES-XTS industry-standard encryption / decryption. Independent non-blocking encryption and decryption channels.

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